Conventional solid state drives implement channel selection using a multiplexer (MUX). Channel selection for the multiplexer is done by using a general purpose input/output (GPIO) pin control. The GPIO pin is controlled by a solid state drive controller (i.e., microcontroller unit) firmware.
Flash memory, such as NAND flash, is controlled by hardware logic. When the memory hardware logic needs to switch NAND flash modules, the hardware logic sends a command to the microcontroller unit (MCU). The MCU firmware sends a control signal to the GPIO pin to select the memory channel. Sending a command from the hardware logic to the MCU and then receiving a control signal from the GPIO pin will cause some delay. The delay has a negative impact on solid state random read/write performance.
It would be desirable to implement a memory channel selection control.